The present invention relates to a memory metal-oxide semiconductor (MOS) device, particularly to a complementary metal-oxide semiconductor (CMOS) dynamic random access memory (RAM), and more particularly to an improvement to sense amplifiers incorporated therein.
FIG. 1 shows a configuration of a prior art shared sense amplifier shown in a periodical Denshi Zairyo (Electronics Materials) January 1986, pp. 41 and 42, particularly FIGS. 4 and 5 therein. As illustrated, it includes bit lines 1, 1', bit lines 7, 7', first and second word lines 2, 2', a column decoder 3, an input/out (I/O) line 4, an I/O line 4', and memory cells M1, M2.
The memory cell M1 comprises a transistor Q1 and a capacitor C1. Similarly, the memory cell M2 comprises a transistor Q2 and a capacitor C2.
FIG. 2 shows a chip architecture of the MOS dynamic RAM employing the sense amplifier configuration of FIG. 1. As illustrated, the chip area includes an area 5 which comprises an area 5a for the sense amplifiers (transistors Q.sub.12 to Q.sub.17), an area 5b for I/O gates (transistors Q.sub.3, Q.sub.4) and an area 5c for bit-line precharge circuits (transistors Q.sub.9 to Q.sub.11). An area 6 is for a row decoder.
In the shared-sense amplifier configuration, one sense amplifier is shared by pairs of bit lines 1, 1' and bit lines 7, 7'. As a result, the chip size and the power consumption can be reduced.
The operation of the memory of FIG. 1 and FIG. 2 will now be described.
The shared-sense amplifier has two operation modes, i.e., a first mode in which a first block A positioned farther away from the column decoder is accessed and a second mode in which a second block B positioned closer to the column decoder is accessed.
First, let us assume that one of the memory cells M1 in the first block A is accessed. It is assumed that the gate signals .phi..sub.GE and .phi..sub.GI are high and the transistors Q.sub.5, Q.sub.6, Q.sub.7 and Q.sub.8 which constitute transfer gates between the bit line pairs 1, 1', 7, 7' and the sense amplifier circuit 5a are therefore conductive so that the bit lines 1 and 7, and the bit lines 1' and 7' are respectively interconnected; and the sense amplifier activation signal .phi..sub.SAP is high and the sense amplifier activation signal .phi..sub.SAN is low so that the sense amplifier circuit 5a is inactive; and the column address signal .phi..sub.Y from the column decoder 3 is low, and the transistors Q3 and Q4 are off, so that the bit lines 1, 1', 7, 7' are disconnected from the I/O lines 4, 4'.
During such time, the transistors Q.sub.9, Q.sub.10 and Q.sub.11 are conductive by the precharge signal .phi..sub.PC and the bit lines 1, 1', 7, 7' are precharged to a preset potential V.sub.BL (which is normally Vcc/2).
Next, the precharge signal .phi..sub.PC goes low, and the transistors Q.sub.9, Q.sub.10 and Q.sub.11 are turned off. Then, the gate signal .phi..sub.GI goes low, to turn off the transistors Q.sub.5 and Q.sub.6 and the bit lines of the unselected block B are therefore disconnected from the sense amplifier circuit. After that, the word line 2 is accessed, and the transistor Q.sub.1 is turned on, so that the data which has been stored in the memory cell M1 is read out onto the bit line 1'. Thereafter, the sense amplifier activation signal .phi..sub.SAP goes low and the sense amplifier activation signal .phi..sub.SAN goes high to activate the sense amplifier, and the data from the memory cell M1 is amplified on the bit lines 1, 1'. The column address signal .phi..sub.Y thereafter goes high to turn on the transistors Q.sub.3 and Q.sub.4, so that the data on the bit lines are read out onto the I/O lines 4, 4'.
For writing data which is an inversion of the data that has just been read through the I/O lines, the new data (inversion) is transmitted from the I/O lines, through the transistors Q.sub.3 and Q.sub.4, to the sense amplifier circuit, the flip-flop associated with the sense amplifier circuit being thereby inverted. The new data is thereby amplified on the bit lines 1, 1' and is written into the memory cell M1.
Similar operations occur when a memory cell M2 in the block B is accessed, and data is written in the memory cell M2.
A disadvantage of the above-described arrangement is explained below:
The column address signal .phi..sub.Y from the column decoder 3 must be supplied from the column decoder 3 situated beyond the end of the bit lines, to the I/O gates (transistors Q.sub.3 and Q.sub.4) within the area 5. Accordingly, it was necessary to dispose a column address signal line (for .phi..sub.Y) to extend between the bit lines, if the column address signal line is formed of the same conductor layer as the bit lines, or to form the column address signal line using a different conductor layer. Moreover, since the column address signal line forms capacitances with the bit lines, it was necessary to make such an arrangement as to avoid imbalance between the capacitances.